MRF24J40_08 Datasheet, PDF (97/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.8.1.2 BO and SO
Values of Beacon Order (BO) and Superframe Order
(SO) determine the Beacon Interval (BI) and
Superframe Duration (SD).
Beacon Interval (BI) in terms of BO can be expressed as:
BI = aBaseSuperframeduration * 2^BO
Similarly, Superframe Duration (SD) in terms of SO can
be expressed as:
SD = aBaseSuperframeduration * 2^SO
where aBaseSuperframeduration = 960 symbols.
BO and SO can be configured by programming the BO
(0x10<7:4>) bits and SO (0x10<3:0>) bits in the ORDER
register. For beacon-enabled networks, the values of BO
and SO should be in the range, 0 ≤ SO ≤ BO ≤ 14. If the
values of BO and SO are equal, then the superframe
does not have any inactive portion. A Beacon Interval
can be as short as 15 μs or a long as 251 seconds based
on the values of BO and SO.
FIGURE 3-5:
GTSFIFO STATE DIAGRAM
3.8.1.3 GTS
If a device wants to transmit or receive during CFP, it
sends out a “GTS request” in the CAP to the PAN coor-
dinator. The PAN coordinator broadcasts the address
of the device number for that device in the beacon
frame if resources are available.
To support GTS operation, MRF24J40 uses
TXGTS1FIFO and TXGTS2FIFO. The TXGTS1FIFO
and TXGTS2FIFO are ping-pong FIFOs and can be
assigned to different GTS slots or to the same slots. If
both are assigned to the same slot, they take turns for
transmission within that slot. TXGTS1FIFO and
TXGTS2FIFO can be triggered ahead of their slot time,
but transmission from the FIFO will take place exactly
at the assigned slot time.
Refer to Section 3.12 “Transmission” for information
on how to transmit a data frame using the
TXGTSxFIFOs.
GTSSWITCH = 1
Switch TXGTSxFIFO
if Transmit Error
Wait for GTS Slot
TXGTS1FIFO
GTSSWITCH = 0
Hold and wait TXGTSxFIFO
if Transmit Error
Wait for GTS Slot
TXGTS1FIFO
Transmit Error
(clear TXG1TRIG
and TXG2TRIG)
Transmit Complete
or
Transmit Error
(clear TXG1TRIG)
Transmit Complete
or
Transmit Error
(clear TXG2TRIG)
Transmit
Complete
Transmit
Complete
Hold and Wait
until Next GTS
Wait for GTS Slot
TXGTS2FIFO
Wait for GTS Slot
TXGTS2FIFO
Transmit Error
(clear TXG1TRIG
and TXG2TRIG)
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 95