MRF24J40_08 Datasheet, PDF (112/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.12.4 TX GTSx FIFO
In Beacon-Enabled mode, the TX GTSx FIFOs are
used for the transmission of data or MAC command
frames during the CFP of the superframe. Refer to
Section 3.8.1 “Beacon-Enabled Network” for more
information about guaranteed time slots in
Beacon-Enabled mode.
To transmit a packet in the TX GTSx FIFO, perform the
following steps:
1. The host processor loads the respective TX
GTSx FIFO with an IEEE 802.15.4 compliant
data or MAC command frame using the format
shown in Figure 3-14.
FIGURE 3-14:
TX GTS1 AND GTS2 FIFOS FORMAT
octets
Packet Structure
1
1
Header Frame
Length Length
(m) (m + n)
m
Header
n
Payload
TX GTS1 FIFO
Memory Address
0x100 0x101 0x102 – (0x102 + m – 1)
(0x102 + m) – (0x102 + m + n – 1)
TX GTS2 FIFO
Memory Address
0x180 0x181 0x182 – (0x182 + m – 1)
(0x182 + m) – (0x182 + m + n – 1)
2. If the packet requires an Acknowledgment, the
Acknowledgment request bit in the frame control
field should be set to ‘1’ in the MAC Header
(MHR) when the host microcontroller loads the
respective TX GTSx FIFO, and set the
TXG1ACKREQ (TXG1CON 0x1C<2>) or
TXG2ACKREQ (TXG2CON 0x1D<2>) bit = 1.
Refer to Section 3.13 “Acknowledgement” for
more information about Acknowledgment
configuration.
3. Program the number of retry times for the
respective TX GTSx FIFO in the TXG1RETRY
(TXG1CON 0x1C<7:6>) or TXG2RETRY
(TXG2CON 0x1D<7:6>) bits.
4. If the frame is to be encrypted, the security
enabled bit in the frame control field should be
set to ‘1’ in the MAC Header (MHR) when the
host microcontroller loads the TX GTSx FIFO,
and set the TXG1SECEN (TXG1CON
0x1C<1>) or TXG2SECEN (TXG2CON
0x1D<1>) bit = 1. Refer to Section 3.17 “Secu-
rity” for more information about Security
modes.
5. Program the slot number for the respective TX
GTSx FIFO in the TXG1SLOT (TXG1CON
0x1C<5:3> or TXG2SLOT (TXG2CON
0x1D<5:3>) bits.
6. Transmit the packet in the respective TX GTSx
FIFO by setting the TXG1TRIG (TXG1CON
0x1C<0>) or TXG2TRIG (TXG2CON 0x1D<0>)
bit = 1. The bit will be automatically cleared by
hardware. The packet will be transmitted at the
corresponding slot time of the superframe.
7. A TXG1IF (INTSTAT 0x31<1>) or TXG2IF
(INTSTAT 0x31<2>) interrupt will be issued. The
TXG1STAT (TXSTAT 0x24<1>) or TXG2STAT
(TXSTAT 0x24<2>) bit indicates the status of the
transmission:
TXGxSTAT = 1: Transmission was successful
TXGxSTAT = 0: Transmission failed, retry
count exceeded
The number of retries of the most recent
transmission is contained in the TXG1RETRY
(TXG1CON 0x1C<7:6>) or TXG2RETRY
(TXG2CON 0x1D<7:6>) bits. The CCAFAIL
(TXSTAT 0x24<5>) bit = 1 indicates if the failed
transmission was due to the channel busy
(CSMA-CA timed out). The TXG1FNT (TXSTAT
0x24<3>) or TXG2FNT (TXSTAT 0x24<4>)
bit = 1 indicates if the TX GTSx FIFO transmis-
sion failed due to not enough time to transmit in
the guaranteed time slot.
DS39776B-page 110
Preliminary
© 2008 Microchip Technology Inc.