MRF24J40_08 Datasheet, PDF (36/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-26: TXG1CON: GTS1 FIFO CONTROL REGISTER (ADDRESS: 0x1C)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN
bit 7
W-0
TXG1TRIG
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
TXG1RETRY<1:0>: TX GTS1 FIFO Retry Times bits
Write: retry times of packet
Read: number of retry times of the successfully transmitted packet
TXG1SLOT<2:0>: GTS Slot that TX GTS1 FIFO Occupies bits
TXG1ACKREQ: TX GTS1 FIFO Acknowledgement Request bit
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXG1SECEN: TX GTS1 FIFO Security Enabled bit
1 = Security enabled
0 = Security disabled (default)
TXG1TRIG: Transmit Frame in TX GTS1 FIFO bit
Transmit the frame in the TX GTS1 FIFO; bit is automatically cleared by hardware.
REGISTER 2-27: TXG2CON: GTS2 FIFO CONTROL REGISTER (ADDRESS: 0x1D)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
W-0
TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
TXG2RETRY<1:0>: TX GTS2 FIFO Retry Times bits
Write: retry times of packet
Read: number of retry times of the successfully transmitted packet
TXG2SLOT<2:0>: GTS Slot that TX GTS2 FIFO Occupies bits
TXG2ACKREQ: TX GTS2 FIFO Acknowledgement Request bit
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXG2SECEN: TX GTS2 FIFO Security Enabled bit
1 = Security enabled
0 = Security disabled (default)
TXG2TRIG: Transmit Frame in TX GTS2 FIFO bit
Transmit the frame in the TX GTS2 FIFO; bit is automatically cleared by hardware.
DS39776B-page 34
Preliminary
© 2008 Microchip Technology Inc.