MRF24J40_08 Datasheet, PDF (12/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
2.13 Serial Peripheral Interface (SPI)
Port Pins
The MRF24J40 communicates with a host micro-
controller via a 4-wire SPI port as a slave device. The
MRF24J40 supports SPI mode 0,0 which requires that
SCK idles in a low state. The CS pin must be held low
while communicating with the MRF24J40. Figure 2-4
shows timing for a write operation. Data is received by
the MRF24J40 via the SDI pin and is clocked in on the
rising edge of SCK. Figure 2-5 shows timing for a read
operation. Data is sent by the MRF24J40 via the SDO
pin and is clocked out on the falling edge of SCK.
Note:
The SDO pin 17 defaults to a low state
when CS is high (the MRF24J40 is not
selected). If the MRF24J40 is to share a
SPI bus, a tri-state buffer should be placed
on the SDO signal to provide a
high-impedance signal to the SPI bus. See
Section 4.4 “MRF24J40 Schematic and
Bill of Materials” for an example
application circuit.
FIGURE 2-4:
SPI PORT WRITE (INPUT) TIMING
CS
SCK
SDI
MSb
LSb
SDO
FIGURE 2-5:
CS
SPI PORT READ (OUTPUT) TIMING
SCK
SDI
SDO
MSb
LSb
DS39776B-page 10
Preliminary
© 2008 Microchip Technology Inc.