MRF24J40_08 Datasheet, PDF (129/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

3.17.4 UPPER LAYER DECRYPTION
To decrypt an upper layer frame, perform the following
steps:
1. The host microcontroller loads the TXNFIFO
with the upper layer frame for decryption into the
TXNFIFO using the format shown in
Figure 3-23. The header length field indicates
the number of octets (bytes) that are not
encrypted.
2. The host microcontroller loads the 13-byte
NONCE value into the UPNONCE12 through
UPNONCE0 (0x240 through 0x24C) registers.
Note:
The header length field, as implemented in
the MRF24J40, is 5-bits long. Therefore,
the header length maximum value is
31 octets (bytes). This conforms to the
IEEE 802.15.4-2003 Specification. How-
ever, it does not conform to the
IEEE 802.15.4-2006 Standard. The work
around is to:
- Use a header length no longer than
31 octets (bytes)
- Implement a security algorithm in the
upper layers
MRF24J40
3. Program the 128-bit security key into the TX
Normal FIFO Security Key FIFO memory
address, 0x280 through 0x28F.
4. Select the security suite and program the
TXNCIPHER (SECCON0 0x2C<2:0>) bits. The
security suite selection values are shown in
Table 3-24.
5. Enable Upper Layer Security Decryption mode by
setting the UPDEC (SECCR2 0x37<7>) bit = 1.
6. Encrypt the frame by setting the TXNTRIG
(TXNCON 0x1B<0>) bit to 1.
7. A TXNIF (INTSTAT 0x31<0>) interrupt will be
issued. The TXNSTAT (TXSTAT 0x24<0>) bit = 0
indicates the encryption has completed.
8. Check if a MIC error occurred by reading the
UPSECERR (0x30<6>) bit:
UPSECERR = 0: No MIC error
UPSECERR = 1: MIC error occurred; write ‘1’
to clear error
9. The decrypted frame is available in the TXNFIFO
and can be read by the host microcontroller.
TABLE 3-26: REGISTERS ASSOCIATED WITH SECURITY
Addr. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1A TXBCON0
r
r
r
r
r
r
TXBSECEN
TXBTRIG
0x1B TXNCON
r
r
r
FPSTAT
INDIRECT TXNACKREQ TXNSECEN
TXNTRIG
0x1C TXG1CON TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG
0x1D TXG2CON TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG
0x24 TXSTAT
TXNRETRY1 TXNRETRY0 CCAFAIL
TXG2FNT
TXG1FNT
TXG2STAT
TXG1STAT
TXNSTAT
0x2C SECCON0 SECIGNORE SECSTART RXCIPHER2 RXCIPHER1 RXCIPHER0 TXNCIPHER2 TXNCIPHER1 TXNCIPHER0
0x2D SECCON1
r
TXBCIPHER2 TXBCIPHER1 TXBCIPHER0
r
r
DISDEC
DISENC
0x30 RXSR
r
UPSECERR BATIND
r
r
r
r
r
0x31 INTSTAT
SLPIF
WAKEIF HSYMTMRIF
SECIF
RXIF
TXG2IF
TXG1IF
TXNIF
0x32 INTCON
SLPIE
WAKEIE HSYMTMRIE
SECIE
RXIE
TXG2IE
TXG1IE
TXNIE
0x37 SECCR2
UPDEC
UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0
0x240 UPNONCE0
UPNONCE<7:0>
0x241 UPNONCE1
UPNONCE<15:8>
0x242 UPNONCE2
UPNONCE<23:16>
0x243 UPNONCE3
UPNONCE<31:24>
0x244 UPNONCE4
UPNONCE<39:32>
0x245 UPNONCE5
UPNONCE<47:40>
0x246 UPNONCE6
UPNONCE<55:48>
0x247 UPNONCE7
UPNONCE<63:56>
0x248 UPNONCE8
UPNONCE<71:64>
0x249 UPNONCE9
UPNONCE<79:72>
0x24A UPNONCE10
UPNONCE<87:80>
0x24B UPNONCE11
UPNONCE<95:88>
0x24C UPNONCE12
UPNONCE<103:96>
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 127