MRF24J40_08 Datasheet, PDF (51/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-45: INTSTAT: INTERRUPT STATUS REGISTER (ADDRESS: 0x31)
RC-0
SLPIF⁽¹⁾
bit 7
RC-0
WAKEIF⁽¹⁾
RC-0
RC-0
HSYMTMRIF⁽¹⁾ SECIF⁽¹⁾
RC-0
RXIF⁽¹⁾
RC-0
TXG2IF⁽¹⁾
RC-0
TXG1IF⁽¹⁾
RC-0
TXNIF⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
RC = Read to clear bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SLPIF: Sleep Alert Interrupt bit⁽¹⁾
1 = Sleep alert interrupt occurred
0 = No Sleep alert interrupt occurred
bit 6
WAKEIF: Wake-up Alert Interrupt bit⁽¹⁾
1 = A wake-up alert interrupt occurred
0 = No wake-up alert interrupt occurred
bit 5
HSYMTMRIF: Half Symbol Timer Interrupt bit⁽¹⁾
1 = A half symbol timer interrupt occurred
0 = No half symbol timer interrupt occurred
bit 4
SECIF: Security Key Request Interrupt bit⁽¹⁾
1 = A security key request interrupt occurred
0 = No security key request interrupt occurred
bit 3
RXIF: RX FIFO Reception Interrupt bit⁽¹⁾
1 = An RX FIFO reception interrupt occurred
0 = No RX FIFO reception interrupt occurred
bit 2
TXG2IF: TX GTS2 FIFO Transmission Interrupt bit⁽¹⁾
1 = A TX GTS2 FIFO transmission interrupt occurred
0 = No TX GTS2 FIFO transmission interrupt occurred
bit 1
TXG1IF: TX GTS1 FIFO Transmission Interrupt bit⁽¹⁾
1 = A TX GTS1 FIFO transmission interrupt occurred
0 = No TX GTS1 FIFO transmission interrupt occurred
bit 0
TXNIF: TX Normal FIFO Release Interrupt bit⁽¹⁾
1 = A TX Normal FIFO transmission interrupt occurred
0 = No TX Normal FIFO transmission interrupt occurred
Note 1: Interrupt bits are cleared to ‘0’ when the INTSTAT register is read.
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 49