MRF24J40_08 Datasheet, PDF (107/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
The RXFIFO is a 128-byte dual port buffer. The
RXMAC circuitry places the packet into the RXFIFO
sequentially, byte by byte, using an internal pointer.
The internal pointer is reset one of three ways:
1. When the host microcontroller reads the first
byte of the packet.
2. Manually by setting the RXFLUSH (0x0D<0>)
bit. The bit is automatically cleared to ‘0’ by
hardware.
3. Software Reset (see Section 3.1 “Reset” for
more information).
The RXFIFO can only hold one packet at a time. It is
highly recommended that the host microcontroller read
the entire RXFIFO without interruption so that received
packets are not missed.
Note:
When the first byte of the RXFIFO is read,
the MRF24J40 is ready to receive the next
packet. To avoid receiving a packet while
the RXFIFO is being read, set the Receive
Decode Inversion (RXDECINV) bit
(0x39<2>) to ‘1’ to disable the MRF24J40
from receiving a packet off the air. Once
the data is read from the RXFIFO, the
RXDECINV should be cleared to ‘0’ to
enable packet reception.
Example 3-2 shows example steps to read the
RXFIFO.
EXAMPLE 3-2: STEPS TO READ RXFIFO
Example steps to read the RXFIFO:
1. Receive RXIF interrupt.
2. Disable host microcontroller interrupts.
3. Set RXDECINV = 1; disable receiving packets off air.
4. Read address, 0x300; get RXFIFO frame length value.
5. Read RXFIFO addresses, 0x301 through (0x300 + Frame Length + 2); read packet data plus LQI and RSSI.
6. Clear RXDECINV = 0; enable receiving packets.
7. Enable host microcontroller interrupts.
3.11.5 SECURITY
If the received packet has the security enabled bit set to
‘1’ (bit 3 of the frame control field; refer to IEEE 802.15.4
Standard, Section 7.2.1.1 “Frame Control Field”) a
Security Interrupt (SECIF 0x31<4>) is issued. The host
microcontroller can then decide to decrypt or ignore the
packet. See Section 3.17 “Security” for more
information.
TABLE 3-15:
Addr. Name
0x00 RXMCR
0x0D RXFLUSH
0x2A SOFTRST
0x31 INSTAT
0x32 INTCON
0x39 BBREG1
REGISTERS ASSOCIATED WITH RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
r
r
r
SLPIF
SLPIE
r
r
WAKEPOL
r
WAKEIF
WAKEIE
r
NOACKRSP
WAKEPAD
r
HSYMTMRIF
HSYMTMRIE
r
r
r
r
SECIF
SECIE
r
PANCOORD
CMDONLY
r
RXIF
RXIE
r
Bit 2
COORD
DATAONLY
RSTPWR
TXG2IF
TXG2IE
RXDECINV
Bit 1
ERRPKT
BCNONLY
RSTBB
TXG1IF
TXG1IE
r
Bit 0
PROMI
RXFLUSH
RSTMAC
TXNIF
TXNIE
r
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 105