MRF24J40_08 Datasheet, PDF (105/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.11 Reception
An IEEE 802.15.4 compliant packet is prefixed with a
Synchronization Header (SHR) containing the
preamble sequence and Start-of-Frame Delimiter
(SFD) fields. The preamble sequence enables the
receiver to achieve symbol synchronization.
The MRF24J40 monitors incoming signals and looks
for the preamble of IEEE 802.15.4 packets. When a
valid synchronization is obtained, the entire packet is
FIGURE 3-9:
PACKET RECEPTION
demodulated and the CRC is calculated and checked.
The packet is accepted or rejected depending on the
reception mode and frame filter, and placed in the
RXFIFO buffer. When the packet is placed in the
RXFIFO, a Receive Interrupt (RXIF 0x31<3>) is issued.
The RXFIFO address mapping is shown in Figure 3-9.
The following sections detail the reception operation of
the MRF24J40.
From
Air
On Air
Packet
PPDU
4
1
1
PHY
Packet Structure
Preamble
SFD
Frame
Length
Packet to RXMAC
SHR
PHR
To
RXFIFO
RXFIFO
RXFIFO Address:
1
Frame
Length
(m+n+2)
0x300
m
Header (MHR)
0x301 to (0x301 + m – 1)
5 - 127
PSDU
PHY Payload
n
Data Payload (MSDU)
(0x301 + m) to (0x301 + m + n – 1)
2
2
octets
LQI RSSI
2
1
1
octets
FCS
LQI
RSSI
(0x301 + m + n + 3)
(0x301 + m + n + 2)
(0x301 + m + n) to (0x301 + m + n + 1)
Fields appended
by RXMAC
Fields removed
by RXMAC
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 103