MRF24J40_08 Datasheet, PDF (17/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
2.15.2 CONTROL REGISTER SUMMARY
TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40
Addr. File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Details
on
Page:
0x00 RXMCR
r
r
0x01 PANIDL
0x02 PANIDH
0x03 SADRL
0x04 SADRH
0x05 EADR0
0x06 EADR1
0x07 EADR2
0x08 EADR3
0x09 EADR4
0x0A EADR5
0x0B EADR6
0x0C EADR7
0x0D RXFLUSH
r
0x0E Reserved
r
WAKEPOL
r
0x0F Reserved
r
r
0x10 ORDER
BO3
BO2
0x11 TXMCR
0x12 ACKTMOUT
0x13 ESLOTG1
0x14 SYMTICKL
NOCSMA
DRPACK
GTS1-3
TICKP7
BATLIFEXT
MAWD6
GTS1-2
TICKP6
0x15 SYMTICKH
0x16 PACON0
TXONT6
PAONT7
TXONT5
PAONT6
0x17 PACON1
r
r
0x18 PACON2
FIFOEN
r
0x19 Reserved
r
r
0x1A TXBCON0
r
r
0x1B TXNCON
r
r
0x1C TXG1CON TXG1RETRY1 TXG1RETRY0
0x1D TXG2CON TXG2RETRY1 TXG2RETRY0
0x1E ESLOTG23
GTS3-3
GTS3-2
0x1F ESLOTG45
0x20 ESLOTG67
GTS5-3
r
GTS5-2
r
0x21 TXPEND
0x22 WAKECON
MLIFS5
IMMWAKE
MLIFS4
REGWAKE
0x23 FRMOFFSET OFFSET7
0x24 TXSTAT
TXNRETRY1
OFFSET6
TXNRETRY0
0x25 TXBCON1
0x26 GATECLK
TXBMSK
r
WU/BCN
r
0x27 TXTIME
TURNTIME3
0x28 HSYMTMRL HSYMTMR7
TURNTIME2
HSYMTMR6
0x29 HSYMTMRH HSYMTMR15 HSYMTMR14
0x2A SOFTRST
r
r
0x2B Reserved
0x2C SECCON0
r
SECIGNORE
r
SECSTART
0x2D SECCON1
0x2E TXSTBL
r
RFSTBL3
TXBCIPHER2
RFSTBL2
0x2F Reserved
r
r
Legend:
r = reserved
NOACKRSP
r
PANCOORD
PAN ID Low Byte (PANIDL<7:0>)
PAN ID High Byte (PANIDH<15:8>)
COORD
Short Address Low Byte (SADRL<7:0>)
Short Address High Byte (SADRH<15:8>)
64-Bit Extended Address bits (EADR0<7:0>)
64-Bit Extended Address bits (EADR1<15:8>)
64-Bit Extended Address bits (EADR2<23:16>)
64-Bit Extended Address bits (EADR3<31:24>)
64-Bit Extended Address bits (EADR4<39:32>)
64-Bit Extended Address bits (EADR5<47:40>)
64-Bit Extended Address bits (EADR6<55:48>)
64-Bit Extended Address bits (EADR7<63:56>)
WAKEPAD
r
CMDONLY
DATAONLY
r
r
r
r
r
r
r
r
BO1
BO0
SO3
SO2
SLOTTED
MAWD5
GTS1-1
TICKP5
MACMINBE1
MAWD4
GTS1-0
TICKP4
MACMINBE0
MAWD3
CAP3
TICKP3
CSMABF2
MAWD2
CAP2
TICKP2
TXONT4
PAONT5
TXONT3
PAONT4
TXONT2
PAONT3
TXONT1
PAONT2
r
TXONTS3
PAONTS3
TXONTS2
PAONTS2
TXONTS1
PAONTS1
TXONTS0
r
r
r
r
r
r
r
r
r
TXG1SLOT2
FPSTAT
TXG1SLOT1
INDIRECT TXNACKREQ
TXG1SLOT0 TXG1ACKREQ
TXG2SLOT2
GTS3-1
TXG2SLOT1
GTS3-0
TXG2SLOT0
GTS2-3
TXG2ACKREQ
GTS2-2
GTS5-1
r
GTS5-0
r
GTS4-3
GTS6-3
GTS4-2
GTS6-2
MLIFS3
r
MLIFS2
r
MLIFS1
r
MLIFS0
r
OFFSET5
CCAFAIL
OFFSET4
TXG2FNT
OFFSET3
TXG1FNT
OFFSET2
TXG2STAT
RSSINUM1
RSSINUM0
r
r
r
r
GTSON
r
TURNTIME1
HSYMTMR5
TURNTIME0
HSYMTMR4
r
HSYMTMR3
r
HSYMTMR2
HSYMTMR13
r
HSYMTMR12
r
HSYMTMR11
r
HSYMTMR10
RSTPWR
r
RXCIPHER2
r
RXCIPHER1
r
RXCIPHER0
r
TXNCIPHER2
TXBCIPHER1
RFSTBL1
TXBCIPHER0
RFSTBL0
r
MSIFS3
r
MSIFS2
r
r
r
r
ERRPKT
BCNONLY
r
r
SO1
CSMABF1
MAWD1
CAP1
TICKP1
TXONT0
PAONT1
PAONTS0
TXONT8
r
TXBSECEN
TXNSECEN
TXG1SECEN
TXG2SECEN
GTS2-1
GTS4-1
GTS6-1
GTSSWITCH
r
OFFSET1
TXG1STAT
r
r
r
HSYMTMR1
HSYMTMR09
RSTBB
r
TXNCIPHER1
DISDEC
MSIFS1
r
PROMI 0000 0000 18
0000 0000 19
0000 0000 19
0000 0000 20
0000 0000 20
0000 0000 21
0000 0000 21
0000 0000 21
0000 0000 22
0000 0000 22
0000 0000 22
0000 0000 23
0000 0000 23
RXFLUSH 0000 0000 24
r
0000 0000 —
r
0000 0000 —
SO0
1111 1111 25
CSMABF0 0001 1100 26
MAWD0 0011 1001 27
CAP0 0000 0000 28
TICKP0 0100 0000 29
TICKP8 0101 0001 29
PAONT0 0010 1001 30
PAONT8 0000 0010 30
TXONT7 1000 1000 31
r
0000 0000 —
TXBTRIG 0000 0000 32
TXNTRIG 0000 0000 33
TXG1TRIG 0000 0000 34
TXG2TRIG 0000 0000 34
GTS2-0 0000 0000 35
GTS4-0 0000 0000 35
GTS6-0 0000 0000 35
FPACK 1000 0100 36
r
0000 0000 37
OFFSET0 0000 0000 38
TXNSTAT 0000 0000 39
r
0011 0000 40
r
0000 0000 41
r
0100 1000 42
HSYMTMR0 0000 0000 43
HSYMTMR08 0000 0000 43
RSTMAC 0000 0000 44
r
0000 0000 —
TXNCIPHER0 0000 0000 45
DISENC 0000 0000 46
MSIFS0 0111 0101 47
r
0000 0000 —
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 15