MRF24J40_08 Datasheet, PDF (65/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-67: SLPCAL0: SLEEP CALIBRATION 0 REGISTER (ADDRESS: 0x209)
R-0
SLPCAL7
bit 7
R-0
SLPCAL6
R-0
SLPCAL5
R-0
R-0
SLPCAL4 SLPCAL3
R-0
SLPCAL2
R-0
SLPCAL1
R-0
SLPCAL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SLPCAL<7:0>: Sleep Calibration Counter bits
20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of
16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL),
RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns).
REGISTER 2-68: SLPCAL1: SLEEP CALIBRATION 1 REGISTER (ADDRESS: 0x20A)
R-0
SLPCAL15
bit 7
R-0
R-0
R-0
R-0
SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11
R-0
SLPCAL10
R-0
SLPCAL9
R-0
SLPCAL8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SLPCAL<15:8>: Sleep Calibration Counter bits
20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of
16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL),
RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns).
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 63