PIC16LF1526 Datasheet, PDF (84/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
7.6.5 PIE4 REGISTER
The PIE4 register contains the interrupt enable bits, as
shown in Register 7-5.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0/0
CCP10IE
bit 7
R/W-0/0
CCP9IE
R-0/0
RC2IE
R-0/0
TX2IE
R/W-0/0
CCP8IE
R/W-0/0
CCP7IE
R/W-0/0
BCL2IE
R/W-0/0
SSP2IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CCP10IE: CCP10 Interrupt Enable bit
1 = Enables the CCP10 interrupt
0 = Disables the CCP10 interrupt
bit 6
CCP9IE: CCP9 Interrupt Enable bit
1 = Enables the CCP9 interrupt
0 = Disables the CCP9 interrupt
bit 5
RC2IE: USART2 Receive Interrupt Enable bit
1 = Enables the USART2 receive interrupt
0 = Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enables the USART2 transmit interrupt
0 = Disables the USART2 transmit interrupt
bit 3
CCP8IE: CCP8 Interrupt Enable bit
1 = Enables the CCP8 interrupt
0 = Disables the CCP8 interrupt
bit 2
CCP7IE: CCP7 Interrupt Enable bit
1 = Enables the CCP7 interrupt
0 = Disables the CCP7 interrupt
bit 1
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt
bit 0
SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt
DS41458A-page 84
Preliminary
 2011 Microchip Technology Inc.