PIC16LF1526 Datasheet, PDF (280/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin
TXx/CKx pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 22-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
266
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
266
INTCON
PIE1
PIE4
PIR1
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
93
TMR1GIE ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
94
CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE
97
TMR1GIF ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
98
PIR4
CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF
97
RC1REG
EUSART1 Receive Register
260*
RC1STA
RC2REG
RC2STA
SP1BRGL
SPEN
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
265
EUSART2 Receive Register
260*
RX9
SREN CREN ADDEN FERR
OERR
RX9D
265
EUSART1 Baud Rate Generator, Low Byte
267*
SP1BRGH
EUSART1 Baud Rate Generator, High Byte
267*
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
267*
SP2BRGH
EUSART2 Baud Rate Generator, High Byte
267*
TX1STA
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
264
TX2STA
Legend:
*
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
264
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
Page provides register information.
DS41458A-page 280
Preliminary
 2011 Microchip Technology Inc.