PIC16LF1526 Datasheet, PDF (82/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
7.6.3 PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
U-0
OSFIE
TMR5GIE TMR3GIE
—
bit 7
R/W-0/0
BCL1IE
R/W-0/0
TMR10IE
R/W-0/0
TMR8IE
R/W-0/0
CCP2IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enables the Timer5 Gate Acquisition interrupt
0 = Disables the Timer5 Gate Acquisition interrupt
bit 5
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enables the Timer3 Gate Acquisition interrupt
0 = Disables the Timer3 Gate Acquisition interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = Enables the MSSP1 Bus Collision Interrupt
0 = Disables the MSSP1 Bus Collision Interrupt
bit 2
TMR10IE: TMR10 to PR10 Match Interrupt Enable bit
1 = Enables the Timer10 to PR10 match interrupt
0 = Disables the Timer10 to PR10 match interrupt
bit 1
TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enables the Timer8 to PR8 match interrupt
0 = Disables the Timer8 to PR8 match interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS41458A-page 82
Preliminary
 2011 Microchip Technology Inc.