PIC16LF1526 Datasheet, PDF (202/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
The I²C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 21-2 is a block diagram of the I²C Interface
module in Master mode. Figure 21-3 is a diagram of the
I²C interface module in Slave mode.
The PIC16F1527 has two MSSP modules, MSSP1 and
MSSP2, each module operating independently from
the other.
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSP1CON1 and SSP1CON2 registers
control different operational aspects of
the same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
2: Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
FIGURE 21-2:
MSSPX BLOCK DIAGRAM (I²C™ MASTER MODE)
SDAx
SCLx
SDAx in
Read
Internal
data bus
Write
SSPxBUF
SSPxSR
MSb
Shift
Clock
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
[SSPxM 3:0]
Baud rate
generator
(SSPxADD)
SCLx in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
DS41458A-page 202
Preliminary
 2011 Microchip Technology Inc.