PIC16LF1526 Datasheet, PDF (83/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
7.6.4 PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0/0
CCP6IE
bit 7
R/W-0/0
CCP5IE
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
R/W-0/0
TMR6IE
R/W-0/0
TMR5IE
R/W-0/0
TMR4IE
R/W-0/0
TMR3IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CCP6IE: CCP6 Interrupt Enable bit
1 = Enables the CCP6 interrupt
0 = Disables the CCP6 interrupt
bit 6
CCP5IE: CCP5 Interrupt Enable bit
1 = Enables the CCP5 interrupt
0 = Disables the CCP5 interrupt
bit 5
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
bit 4
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
bit 3
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
bit 2
TMR5IE: Timer5 Overflow Interrupt Enable bit
1 = Enables the Timer5 overflow interrupt
0 = Disables the Timer5 overflow interrupt
bit 1
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
bit 0
TMR3IE: Timer3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overflow interrupt
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 83