PIC16LF1526 Datasheet, PDF (137/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

12.8 PORTG Registers
PORTG is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISG
(Register 12-3). Setting a TRISG bit (= 1) will make the
corresponding PORTG pin an input (i.e., disable the
output driver). Clearing a TRISG bit (= 0) will make the
corresponding PORTG pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RG5, which is
input only and its TRIS bit will always read as ‘1’.
Example 12-1 shows how to initialize an I/O port.
Reading the PORTG register (Register 12-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATG).
The TRISG register (Register 12-3) controls the
PORTG pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISG register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
12.8.1 ANSELG REGISTER
The ANSELG register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELG bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELG bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELG bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
PIC16(L)F1526/27
12.8.2
PORTG FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTG pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-16.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, are not shown in
the priority lists. These inputs are active when the I/O
pin is set for Analog mode using the ANSELx registers.
Digital output functions may control the pin when it is in
Analog mode with Table 12-16.
TABLE 12-16: PORTG OUTPUT PRIORITY
Pin Name
Function Priority⁽¹⁾
RG0
CCP3
RG0
RG1
CK2
TX2
RG1
RG2
DT2
RG2
RG3
CCP4
RG3
RG4
CCP5
RG4
RG5
Input only pin
Note 1: Priority listed from highest to lowest.
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 137