PIC16LF1526 Datasheet, PDF (178/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
18.12.1 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2 ANSA1 ANSA0
APFCON
—
—
—
—
—
—
T3CKISEL CCP2SEL
CCP1CON
—
—
DC1B<1:0>
CCP1M<3:0>
CCP2CON
—
—
DC2B<1:0>
CCP2M<3:0>
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
CCP5CON
—
—
DC5B<1:0>
CCP5M<3:0>
CCP6CON
—
—
DC6B<1:0>
CCP6M<3:0>
CCP7CON
—
—
DC7B<1:0>
CCP7M<3:0>
CCP8CON
—
—
DC8B<1:0>
CCP8M<3:0>
CCP9CON
—
—
DC9B<1:0>
CCP9M<3:0>
CCP10CON
—
—
DC10B<1:0>
CCP10M<3:0>
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RC1IE
TX1IE
SSP1IE CCP1IE TMR2IE TMR1IE
PIE2
OSFIE TMR5GIE TMR3GIE
—
BCL1IE TMR10IE TMR8IE CCP2IE
PIE3
CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE
PIR1
TMR1GIF
ADIF
RC1IF
TX1IF
SSP1IF CCP1IF TMR2IF TMR1IF
PIR2
OSFIF TMR5GIF TMR3GIF
—
BCL1IF TMR10IF TMR8IF CCP2IF
PIR3
CCP6IF
CCP5IF
CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR5L
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
TRISA
TRISA7
TRISA6
TRISA5 TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
SOSCEN T1SYNC
—
TMR1ON
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
SOSCEN T3SYNC
—
TMR3ON
T5CON
TMR5CS<1:0>
T5CKPS<1:0>
SOSCEN T5SYNC
—
TMR5ON
T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
T3GCON
TMR3GE T3GPOL
T3GTM
T3GSPM
T3GGO/
DONE
T3GVAL
T3GSS<1:0>
T5GCON
TMR5GE T5GPOL
T5GTM
T5GSPM
T5GGO/
DONE
T5GVAL
T5GSS<1:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1/3/5 module.
* Page provides register information.
Register
on Page
121
118
197
197
197
197
197
197
197
197
197
197
80
81
82
83
85
86
87
172*
172*
172*
172*
172*
172*
120
176
176
176
177
177
177
DS41458A-page 178
Preliminary
 2011 Microchip Technology Inc.