PIC16LF1526 Datasheet, PDF (190/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
—
—
—
—
CCP1CON
—
—
DC1B<1:0>
—
—
T3CKISEL CCP2SEL
CCP1M<3:0>
CCP2CON
—
—
DC2B<1:0>
CCP2M<3:0>
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
CCP5CON
—
—
DC5B<1:0>
CCP5M<3:0>
CCP6CON
—
—
DC6B<1:0>
CCP6M<3:0>
CCP7CON
—
—
DC7B<1:0>
CCP7M<3:0>
CCP8CON
—
—
DC8B<1:0>
CCP8M<3:0>
CCP9CON
—
—
DC9B<1:0>
CCP9M<3:0>
CCP10CON
—
—
DC10B<1:0>
CCP10M<3:0>
CCPR1L
Capture/Compare/PWM Register 1 Low Byte (LSB)
CCPR2L
Capture/Compare/PWM Register 2 Low Byte (LSB)
CCPR3L
Capture/Compare/PWM Register 3 Low Byte (LSB)
CCPR4L
Capture/Compare/PWM Register 4 Low Byte (LSB)
CCPR5L
Capture/Compare/PWM Register 5 Low Byte (LSB)
CCPR6L
Capture/Compare/PWM Register 6 Low Byte (LSB)
CCPR7L
Capture/Compare/PWM Register 7 Low Byte (LSB)
CCPR8L
Capture/Compare/PWM Register 8 Low Byte (LSB)
CCPR9L
Capture/Compare/PWM Register 9 Low Byte (LSB)
CCPR10L Capture/Compare/PWM Register 10 Low Byte (LSB)
CCPR1H
Capture/Compare/PWM Register 1 High Byte (MSB)
CCPR2H
Capture/Compare/PWM Register 2 High Byte (MSB)
CCPR3H
Capture/Compare/PWM Register 3 High Byte (MSB)
CCPR4H
Capture/Compare/PWM Register 4 High Byte (MSB)
CCPR5H
Capture/Compare/PWM Register 5 High Byte (MSB)
CCPR6H
Capture/Compare/PWM Register 6 High Byte (MSB)
CCPR7H
Capture/Compare/PWM Register 7 High Byte (MSB)
CCPR8H
Capture/Compare/PWM Register 8 High Byte (MSB)
CCPR9H
Capture/Compare/PWM Register 9 High Byte (MSB)
CCPR10H Capture/Compare/PWM Register 10 High Byte (MSB)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSFIE
TMR5GIE TMR3GIE
—
BCL1IE
TMR10IE TMR8IE
CCP2IE
PIE3
CCP6IE
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR5IE
TMR4IE
TMR3IE
PIE4
CCP10IE CCP9IE
RC2IE
TX2IE
CCP8IE
CCP7IE
BCL2IE
SSP2IE
PIR1
TMR1GIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR2
OSFIF
TMR5GIF TMR3GIF
—
BCL1IF
TMR10IF
TMR8IF
CCP2IF
PIR3
CCP6IF
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR5IF
TMR4IF
TMR3IF
PIR4
CCP10IF
CCP9IF
RC2IF
TX2IF
CCP8IF
CCP7IF
BCL2IF
SSP2IF
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
SOSCEN
T1SYNC
—
TMR1ON
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
SOSCEN
T3SYNC
—
TMR3ON
T5CON
TMR5CS<1:0>
T5CKPS<1:0>
SOSCEN
T5SYNC
—
TMR5ON
T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
T3GCON
TMR3GE T3GPOL
T3GTM
T3GSPM T3GGO/DONE T3GVAL
T3GSS<1:0>
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
* Page provides register information.
Register on
Page
118
197
197
197
197
197
197
197
197
197
197
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
184*
80
81
82
83
84
85
86
87
88
176
176
176
177
177
DS41458A-page 190
Preliminary
 2011 Microchip Technology Inc.