PIC16LF1526 Datasheet, PDF (170/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
18.3 Timer1/3/5 Prescaler
Timer1/3/5 has four prescaler options allowing 1, 2, 4 or
8 divisions of the clock input. The TxCKPS bits of the
TxCON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMRxH or TMRxL.
18.4 Timer1/3/5 Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins SOSCI (input) and SOSCO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the SOSCEN
bit of the TxCON register. The oscillator will continue to
run during Sleep.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
SOSCEN should be set and a suitable
delay observed prior to enabling
Timer1/3/5.
18.5 Timer1/3/5 Operation in
Asynchronous Counter Mode
If control bit TxSYNC of the TxCON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 18.5.1 “Reading and Writing Timer1/3/5 in
Asynchronous Counter Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
18.5.1
READING AND WRITING
TIMER1/3/5 IN ASYNCHRONOUS
COUNTER MODE
Reading TMRxH or TMRxL while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMRxH:TMRxL register pair.
18.6 Timer1/3/5 Gate
Timer1/3/5 can be configured to count freely or the
count can be enabled and disabled using Timer1/3/5
gate circuitry. This is also referred to as Timer1/3/5
Gate Enable.
Timer1/3/5 gate can also be driven by multiple select-
able sources.
18.6.1 TIMER1/3/5 GATE ENABLE
The Timer1/3/5 Gate Enable mode is enabled by set-
ting the TMRxGE bit of the TxGCON register. The
polarity of the Timer1/3/5 Gate Enable mode is config-
ured using the TxGPOL bit of the TxGCON register.
When Timer1/3/5 Gate Enable mode is enabled,
Timer1/3/5 will increment on the rising edge of the
Timer1/3/5 clock source. When Timer1/3/5 Gate
Enable mode is disabled, no incrementing will occur
and Timer1/3/5 will hold the current count. See
Figure 18-4 for timing details.
TABLE 18-3: TIMER1/3/5 GATE ENABLE
SELECTIONS
TxCLK TxGPOL TxG
Timer1/3/5
Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
DS41458A-page 170
Preliminary
 2011 Microchip Technology Inc.