PIC16LF1526 Datasheet, PDF (27/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP (CONTINUED)
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
800h
80Bh
80Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
880h
88Bh
88Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
900h
90Bh
90Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
980h
98Bh
98Ch
Core Registers
(Table 3-2)
A00h
A0Bh
A0Ch
Core Registers
(Table 3-2)
A80h
A8Bh
A8Ch
Core Registers
(Table 3-2)
B00h
B0Bh
B0Ch
Core Registers
(Table 3-2)
B80h
B8Bh
B8Ch
Core Registers
(Table 3-2)
81Fh
820h
86Fh
870h
87Fh
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
89Fh
8A0h
8EFh
8F0h
8FFh
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
91Fh
920h
96Fh
970h
97Fh
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
9EFh
9F0h
9FFh
Common RAM
(Accesses
70h – 7Fh)
A6Fh
A70h
A7Fh
Common RAM
(Accesses
70h – 7Fh)
AEFh
AF0h
AFFh
Common RAM
(Accesses
70h – 7Fh)
B6Fh
B70h
B7Fh
Common RAM
(Accesses
70h – 7Fh)
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h – 7Fh)
C00h
C0Bh
C0Ch
C6Fh
C70h
C7Fh
BANK 24
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
C80h
C8Bh
C8Ch
CEFh
CF0h
CFFh
BANK 25
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D00h
D0Bh
D0Ch
D6Fh
D70h
D7Fh
BANK 26
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D80h
D8Bh
D8Ch
DEFh
DF0h
DFFh
BANK 27
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E00h
E0Bh
E0Ch
E6Fh
E70h
E7Fh
BANK 28
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E80h
E8Bh
E8Ch
EEFh
EF0h
EFFh
BANK 29
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
F00h
F0Bh
F0Ch
F6Fh
F70h
F7Fh
BANK 30
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1: PIC16(L)F1527 only.