PIC16LF1526 Datasheet, PDF (167/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
18.0 TIMER1/3/5 MODULE WITH
GATE CONTROL
The Timer1/3/5 module is a 16-bit timer/counter with
the following features:
• 16-bit timer/counter register pair (TMRxH:TMRxL)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1/3/5 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 18-1 is a block diagram of the Timer1/3/5 module.
.
Note:
The ‘x’ variable used in this section is
used to designate Timer1, Timer3 or
Timer5. For example, TxCON references
T1CON, T3CON or T5CON. PRx refer-
ences PR1, PR3 or PR5.
FIGURE 18-1:
TIMER1/3/5 BLOCK DIAGRAM
TxGSS<1:0>
TxG
00
TxGSPM
From Timer0
Overflow
Timer2/4/6
Overflow⁽⁴⁾
Timer10
Overflow
01
10
11
TxGPOL
Set flag bit
TMRxIF on
Overflow
TxG_IN
0
DQ
1
Single Pulse
Acq. Control
0
TxGVAL _{D Q}
1
Q1 EN
Data Bus
RD
T1GCON
TMRxON
TxGTM
CK ^Q
R
TxGGO/DONE
Interrupt
det
TMRxGE
Set
TMRxGIF
TMRx⁽²⁾
TMRxH
TMRxL
TMRxON
EN
0
Q D ^TxCLK
To Comparator Module
Synchronized
clock input
TMRxCS<1:0>
1
TxSYNC
Secondary Oscillator
(See Figure 18-2)
LFINTOSC 11
SOSC/TxCKI
10
FOSC
Internal ⁰¹
Clock
FOSC/4
Internal ⁰⁰
Clock
Prescaler
1, 2, 4, 8
2
TxCKPS<1:0>
Synchronize⁽³⁾
det
FOSC/2
Internal
Clock
Sleep input
Note 1:
2:
3:
4:
ST Buffer is high-speed type when using TxCKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
See Table 18-4 for Timer selection.
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 167