PIC16LF1526 Datasheet, PDF (26/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP (CONTINUED)
400h
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
46Fh
470h
47Fh
BANK 8
Core Registers
(Table 3-2)
ANSELF
ANSELG
—
—
—
TMR3L
TMR3H
T3CON
T3GCON
TMR4
PR4
T4CON
TMR5L
TMR5H
T5CON
T5GCON
TMR6
PR6
T6CON
—
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
BANK 9
480h
Core Registers
(Table 3-2)
500h
48Bh
50Bh
48Ch
—
50Ch
48Dh
WPUG
48Eh
—
48Fh
—
490h
—
491h
RC2REG
492h
TX2REG
493h
SP2BRG
494h SP2BRGH
495h
RC2STA
496h
TX2STA
497h BAUD2CON
498h
—
499h
—
49Ah
—
49Bh
—
49Ch
—
49Dh
—
49Eh
—
49Fh
4A0h
4BFh
—
General Purpose
Register
32 Bytes
51Fh
520h
4C0h
4EFh
4F0h
4FFh
General Purpose
Register
48 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
56Fh
570h
57Fh
BANK 10
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
580h
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
5FFh
BANK 11
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
TMR8
PR8
T8CON
—
—
—
—
TMR10
PR10
T10CON
—
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
600h
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
67Fh
BANK 12
Core Registers
(Table 3-2)
—
—
—
—
—
CCPR6L
CCPR6H
CCP6CON
CCPR7L
CCPR7H
CCP7CON
CCPR8L
CCPR8H
CCP8CON
CCPR9L
CCPR9H
CCP9CON
CCPR10L
CCPR10H
CCP10CON
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
680h
68Bh
68Ch
69Fh
6A0h
6EFh
6F0h
6FFh
BANK 13
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
700h
70Bh
70Ch
71Fh
720h
76Fh
770h
77Fh
BANK 14
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
780h
78Bh
78Ch
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 15
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes⁽¹⁾
Common RAM
(Accesses
70h – 7Fh)
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1527 only.