PIC16LF1526 Datasheet, PDF (263/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
FIGURE 22-5:
RXx/DTx pin
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCxREG
Start
bit 7/8 Stop bit
bit
Word 2
RCxREG
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 22-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
PIE4
CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE
PIR1
TMR1GIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIR4
CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF
RC1REG
EUSART1 Receive Register
RC1STA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
RC2REG
EUSART2 Receive Register
RC2STA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
SP1BRGL
EUSART1 Baud Rate Generator, Low Byte
SP1BRGH
EUSART1 Baud Rate Generator, High Byte
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
SP2BRGH
EUSART2 Baud Rate Generator, High Byte
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX1STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
TX2STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
* Page provides register information.
Register
on Page
266
266
93
94
97
98
97
260*
265
260*
265
267*
267*
267*
267*
134
264
264
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 263