PIC16LF1526 Datasheet, PDF (171/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
18.6.2
TIMER1/3/5 GATE SOURCE
SELECTION
The Timer1/3/5 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
TABLE 18-4: TIMER1/3/5 GATE SOURCES
T1GSS
Timer1 Gate Source
Timer3 Gate Source
Timer5 Gate Source
00 T1G Pin
T3G Pin
T5G Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10 Timer2 match PR2
Timer4 match PR4
(TMR2 increments to match PR2)
Timer6 match PR6
11
Timer10 match PR10
18.6.2.1 TxG Pin Gate Operation
The TxG pin is one source for Timer1/3/5 gate control.
It can be used to supply an external source to the
Timer1/3/5 gate circuitry.
18.6.2.2 Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1/3/5 gate circuitry.
18.6.3 TIMER1/3/5 GATE TOGGLE MODE
When Timer1/3/5 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1/3/5 gate signal, as opposed to the duration of a
single level pulse.
The Timer1/3/5 gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 18-5 for timing details.
Timer1/3/5 Gate Toggle mode is enabled by setting the
TxGTM bit of the TxGCON register. When the TxGTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
18.6.4
TIMER1/3/5 GATE SINGLE-PULSE
MODE
When Timer1/3/5 Gate Single-Pulse mode is enabled, it
is possible to capture a single pulse gate event.
Timer1/3/5 Gate Single-Pulse mode is first enabled by
setting the TxGSPM bit in the TxGCON register. Next,
the TxGGO/DONE bit in the TxGCON register must be
set. The Timer1/3/5 will be fully enabled on the next
incrementing edge. On the next trailing edge of the pulse,
the TxGGO/DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer1/3/5
until the TxGGO/DONE bit is once again set in software.
See Figure 18-6 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
TxGSPM bit in the TxGCON register, the TxGGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3/5
gate source to be measured. See Figure 18-7 for timing
details.
18.6.5 TIMER1/3/5 GATE VALUE STATUS
When Timer1/3/5 Gate Value Status is utilized, it is pos-
sible to read the most current level of the gate control
value. The value is stored in the TxGVAL bit in the
TxGCON register. The TxGVAL bit is valid even when
the Timer1/3/5 gate is not enabled (TMRxGE bit is
cleared).
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 171