PIC16LF1526 Datasheet, PDF (188/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
20.2 Compare Mode
The Compare mode function described in this section
is available and identical for CCP modules.
Compare mode makes use of the 16-bit Timer1/3/5
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMRxH:TMRxL register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 20-2 shows a simplified diagram of the
Compare operation.
FIGURE 20-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxM<3:0>
Mode Select
CCPx
Pin
Set CCPxIF Interrupt Flag
4 ^(PIRx)
CCPRxH CCPRxL
Q S _Output
R ^Logic
Match
Comparator
TRIS
Output Enable
TMRxH TMRxL
Special Event Trigger
20.2.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
20.2.2 TIMER1/3/5 MODE RESOURCE
In Compare mode, Timer1/3/5 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
TABLE 20-3: CCPx COMPARE TIMER1/3/5
RESOURCES
CCP
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
CCP8
CCP9
CCP10
TMR1
●
●
●
●
●
●
●
●
●
●
TMR3
●
●
●
●
●
TMR5
●
●
●
●
●
See Section 18.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring
Timer1/3/5.
Note:
Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
DS41458A-page 188
Preliminary
 2011 Microchip Technology Inc.