PIC16LF1526 Datasheet, PDF (211/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
21.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELF
ANSF7
ANSF6
ANSF5
ANSF4
ANSF3
ANSF2
ANSF1
ANSF0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE TMR2IE TMR1IE
PIE4
CCP10IE CCP9IE
RC2IE
TX2IE
CCP8IE CCP7IE BCL2IE SSP2IE
PIR1
TMR1GIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF TMR2IF TMR1IF
PIR4
CCP10IF CCP9IF
RC2IF
TX2IF
CCP8IF
CCP7IF
BCL2IF
SSP2IF
SSP1BUF MSSPx Receive Buffer/Transmit Register
SSP2BUF MSSPx Receive Buffer/Transmit Register
SSP1CON1 WCOL
SSPOV SSPEN
CKP
SSP2CON1 WCOL
SSPOV SSPEN
CKP
SSP1CON3 ACKTIM
PCIE
SCIE
BOEN
SSP2CON3 ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
SMP
CKE
D/A
P
SSP2STAT
SMP
CKE
D/A
P
TRISC
TRISC7 TRISC6 TRISC5 TRISC4
SDAHT
SDAHT
S
S
TRISC3
SSPM<3:0>
SSPM<3:0>
SBCDE
AHEN
SBCDE
AHEN
R/W
UA
R/W
UA
TRISC2 TRISC1
DHEN
DHEN
BF
BF
TRISC0
TRISD
TRISD7
TRISD6
TRISD5 TRISD4
TRISD3
TRISD2 TRISD1 TRISD0
TRISF
TRISF7 TRISF6 TRISF5 TRISF4
TRISF3
TRISF2 TRISF1 TRISF0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
* Page provides register information.
Register
on Page
136
80
81
84
85
88
205*
205*
251
251
253
253
249
249
126
129
135
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 211