PIC16LF1526 Datasheet, PDF (195/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
20.3.7 OPERATION IN SLEEP MODE
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
20.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
20.3.9 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
20.3.10 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 20-9: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
—
—
—
—
—
—
T3CKISEL CCP2SEL
CCP1CON
—
—
DC1B<1:0>
CCP1M<3:0>
CCP2CON
—
—
DC2B<1:0>
CCP2M<3:0>
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
CCP5CON
—
—
DC5B<1:0>
CCP5M<3:0>
CCP6CON
—
—
DC6B<1:0>
CCP6M<3:0>
CCP7CON
—
—
DC7B<1:0>
CCP7M<3:0>
CCP8CON
—
—
DC8B<1:0>
CCP8M<3:0>
CCP9CON
—
—
DC9B<1:0>
CCP9M<3:0>
CCP10CON
—
—
DC10B<1:0>
CCP10M<3:0>
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RC1IE
TX1IE
SSP1IE CCP1IE TMR2IE TMR1IE
PIE2
OSFIE TMR5GIE TMR3GIE
—
BCL1IE TMR10IE TMR8IE CCP2IE
PIE3
CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE
PIE4
CCP10IE CCP9IE
RC2IE
TX2IE
CCP8IE CCP7IE BCL2IE SSP2IE
PIR1
TMR1GIF
ADIF
RC1IF
TX1IF
SSP1IF CCP1IF TMR2IF TMR1IF
PIR2
OSFIF TMR5GIF TMR3GIF
—
BCL1IF TMR10IF TMR8IF CCP2IF
PIR3
CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF
PIR4
CCP10IF CCP9IF
RC2IF
TX2IF
CCP8IF CCP7IF BCL2IF SSP2IF
PR2
PR4
PR6
PR8
PR10
T2CON
Timer2 Period Register
Timer4 Period Register
Timer6 Period Register
Timer8 Period Register
Timer10 Period Register
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<:0>1
T4CON
—
T4OUTPS<3:0>
TMR4ON
T4CKPS<:0>1
T6CON
—
T6OUTPS<3:0>
TMR6ON
T6CKPS<:0>1
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Register
on Page
118
197
197
197
197
197
197
197
197
197
197
80
81
82
83
84
85
86
87
88
179*
179*
179*
179*
179*
176
176
176
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 195