PIC16LF1526 Datasheet, PDF (184/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
20.1 Capture Mode
The Capture mode function described in this section is
available and identical for CCP modules.
Capture mode makes use of the 16-bit Timer1/3/5
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMRxH:TMRxL register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 20-1 shows a simplified diagram of the Capture
operation.
20.1.1 CCP PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP2x pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 20-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPx
Pin
Set Flag bit CCPxIF
Prescaler ^{(PIRx register)}
 1, 4, 16
CCPRxH
CCPRxL
and
Edge Detect
Capture
Enable
CCPxM<3:0>
System Clock (FOSC)
TMRxH
TMRxL
20.1.2 TIMER1/3/5 MODE RESOURCE
Timer1/3/5 must be running in Timer mode or
Synchronized Counter mode for the CCP module to use
the capture feature. In Asynchronous Counter mode, the
capture operation may not work.
See Section 18.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring
Timer1/3/5.
TABLE 20-1:
CCP
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
CCP8
CCP9
CCP10
CCPx CAPTURE TIMER1/3/5
RESOURCES
TMR1
TMR3
TMR5
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
20.1.3 SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
Note:
Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
DS41458A-page 184
Preliminary
 2011 Microchip Technology Inc.