PIC16LF1526 Datasheet, PDF (283/354 Pages) Microchip Technology – 64-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1526/27
22.5.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 22.5.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
22.5.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCxIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
266
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
266
INTCON
PIE1
PIE4
PIR1
GIE
PEIE
TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
93
TMR1GIE ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
94
CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE
97
TMR1GIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
98
PIR4
CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF
97
RC1REG
EUSART1 Receive Register
260*
RC1STA
RC2REG
RC2STA
SP1BRGL
SPEN
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
265
EUSART2 Receive Register
260*
RX9
SREN CREN ADDEN FERR
OERR
RX9D
265
EUSART1 Baud Rate Generator, Low Byte
267*
SP1BRGH
EUSART1 Baud Rate Generator, High Byte
267*
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
267*
SP2BRGH
EUSART2 Baud Rate Generator, High Byte
267*
TX1STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
264
TX2STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
264
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
* Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41458A-page 283