PIC17C7XX Datasheet, PDF (72/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
10.2 PORTB and DDRB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRB. A '1' in DDRB
configures the corresponding port pin as an input. A '0'
in the DDRB register configures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to PORTB will write to the port
latch.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any reset.
PORTB also has an interrupt on change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin configured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” out-
puts of RB7:RB0 are OR’ed together to set the PORTB
Interrupt Flag bit, RBIF (PIR1<7>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt by:
a) Read-Write PORTB (such as; MOVPF PORTB,
PORTB). This will end mismatch condition.
b) Then, clear the RBIF bit.
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on this port, allows easy
interface to a keypad and make it possible for wake-up
on key-depression. For an example, refer to Applica-
tion Note AN552, “Implementing Wake-up on Key-
stroke.”
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operations.
Note:
On a device reset, the RBIF bit is indeter-
minate since the value in the latch may be
different than the pin.
FIGURE 10-5: BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS
Weak
Pull-Up
Port
Input Latch
Match Signal
from other
port pins
Peripheral Data in
RBPU (PORTA<7>)
RBIF
Data Bus
RD_DDRB (Q2)
OE
Port
Data
Note: I/O pins have protection diodes to VDD and VSS.
D
Q
CK
D
Q
CK
RD_PORTB (Q2)
WR_DDRB (Q4)
WR_PORTB (Q4)
DS30289A-page 72
© 1998 Microchip Technology Inc.