PIC17C7XX Datasheet, PDF (285/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
APPENDIX E: I²C OVERVIEW
This section provides an overview of the Inter-Inte-
grated Circuit (I²C) bus, with Section 15.2 discussing
the operation of the SSP module in I²C mode.
The I²C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to
100 Kbps. This device will communicate with fast mode
devices if attached to the same bus.
The I²C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, including general call support. Table E-1 defines
some of the I²C bus terminology. For additional infor-
mation on the I²C interface specification, refer to the
Philips document “The I²C bus and how to use it.”
#939839340011, which can be obtained from the Phil-
ips Corporation.
In the I²C interface protocol each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is they can be thought of as operating in either
of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
TABLE E-1: I²C BUS TERMINOLOGY
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I²C bus is
limited only by the maximum bus loading specification
of 400 pF.
E.1 Initiating and Terminating Data
Transfer
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure E-1 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE E-1: START AND STOP
CONDITIONS
SDA
SCL S
Start
Change
Condition of Data
Allowed
P
Change Stop
of Data Condition
Allowed
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization Procedure where the clock signals of two or more devices are synchronized.
© 1998 Microchip Technology Inc.
DS30289A-page 285