PIC17C7XX Datasheet, PDF (255/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

FIGURE 20-12: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
71
72
SCK
(CKP = 1)
80
PIC17C7XX
83
SDO
SDI
MSb
BIT6 - - - - - -1
LSb
75, 76
77
MSb IN
BIT6 - - - -1
LSb IN
74
Refer to Figure 20-1 for load conditions.
TABLE 20-12: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
70 ^{TssL2scH, SS↓ to SCK↓ or SCK↑ input}
TssL2scL
TCY *
— — ns
71 ^TscH
71A
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 * — — ns
Single Byte
40
— — ns Note 1
72 ^TscL
72A
SCK input low time
(slave mode)
Continuous 1.25TCY + 30 * — — ns
Single Byte
40
— — ns Note 1
73A ^TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 * — — ns Note 1
edge of Byte2
74 ^{TscH2diL, Hold time of SDI data input to SCK edge}
TscL2diL
100 *
— — ns
75 ^TdoR
SDO data output rise time
—
10 25 * ns
76 ^TdoF
SDO data output fall time
—
10 25 * ns
77 ^{TssH2doZ SS↑ to SDO output hi-impedance}
10 *
— 50 * ns
80 ^{TscH2doV, SDO data output valid after SCK edge}
TscL2doV
—
— 50 * ns
82 ^{TssL2doV SDO data output valid after SS↓ edge}
—
— 50 * ns
83 ^{TscH2ssH, SS ↑ after SCK edge}
TscL2ssH
1.5TCY + 40 * — — ns
*
Characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
© 1998 Microchip Technology Inc.
Preliminary
DS30289A-page 255