PIC17C7XX Datasheet, PDF (47/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
TABLE 7-3: SPECIAL FUNCTION REGISTERS (Cont.’d)
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
MCLR,
WDT
Bank 2
10h
11h
12h
13h
14h
15h
16h
17h
TMR1
TMR2
TMR3L
TMR3H
PR1
PR2
PR3L/CA1L
PR3H/CA1H
Timer1’s register
Timer2’s register
Timer3’s register; low byte
Timer3’s register; high byte
Timer1’s period register
Timer2’s period register
Timer3’s period register - low byte/capture1 register; low byte
Timer3’s period register - high byte/capture1 register; high byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Bank 3
10h
11h
12h
13h
14h
15h
16h
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
CA2H
TCON1
DC1
DC0
—
DC1
DC0 TM2PW2
DC9
DC8
DC7
DC9
DC8
DC7
Capture2 low byte
Capture2 high byte
CA2ED1 CA2ED0 CA1ED1
—
—
DC6
DC6
CA1ED0
—
—
DC5
DC5
T16
—
—
DC4
DC4
TMR3CS
—
—
DC3
DC3
TMR2CS
— xx-- ---- uu-- ----
— xx0- ---- uu0- ----
DC2 xxxx xxxx uuuu uuuu
DC2 xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1CS 0000 0000 0000 0000
17h TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4:
10h
PIR2
SSPIF BCLIF ADIF
—
CA4IF CA3IF
TX2IF
RC2IF 000- 0010 000- 0010
11h
PIE2
SSPIE BCLIE ADIE
—
CA4IE CA3IE
TX2IE
RC2IE 000- 0000 000- 0000
12h
Unimple-
—
—
—
—
—
—
—
— ---- ---- ---- ----
mented
13h
RCSTA2
SPEN RX9
SREN
CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00u
14h
RCREG2
Serial Port Receive Register for USART2
xxxx xxxx uuuu uuuu
15h
TXSTA2
CSRC TX9
TXEN
SYNC
—
—
TRMT
TX9D 0000 --1x 0000 --1u
16h
TXREG2
Serial Port Transmit Register for USART2
xxxx xxxx uuuu uuuu
17h
SPBRG2
Baud Rate Generator for USART2
0000 0000 0000 0000
Bank 5:
10h
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
11h
PORTF ⁽⁴⁾
RF7/
RF6/
RF5/
RF4/
RF3/
RF2/
RF1/
RF0/
AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4 ^{0000 0000 0000 0000}
12h
DDRG
Data Direction Register for PORTG
1111 1111 1111 1111
13h
PORTG ⁽⁴⁾
RG7/ RG6/
RG5/
TX2/CK2 RX2/DT2 PWM3
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
xxxx 0000 uuuu 0000
14h
ADCON0
CHS3 CHS2 CHS1
CHS0
— GO/DONE
—
ADON 0000 -0-0 0000 -0-0
15h
ADCON1
ADCS1 ADCS0 ADFM
—
PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h
ADRESL
A/D Result Register low byte
xxxx xxxx uuuu uuuu
17h
ADRESH
A/D Result Register high byte
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>
whose contents are updated from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or extended microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device reset, these pins are configured as inputs.
© 1998 Microchip Technology Inc.
DS30289A-page 47