PIC17C7XX Datasheet, PDF (53/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

7.4 Indirect Addressing
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to
be read or written can be modified by the program.
This can be useful for data tables in the data memory.
Figure 7-9 shows the operation of indirect addressing.
This depicts the moving of the value to the data mem-
ory address specified by the value of the FSR register.
Example 7-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined num-
ber of bytes (block) of data to the USART transmit reg-
ister (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
FIGURE 7-9: INDIRECT ADDRESSING
RAM
Instruction
Executed
Opcode
Address
8
File = INDFx
Instruction
Fetched
Opcode
88
File
FSR
7.4.1 INDIRECT ADDRESSING REGISTERS
The PIC17C7XX has four registers for indirect
addressing. These registers are:
• INDF0 and FSR0
• INDF1 and FSR1
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers acti-
vates indirect addressing, with the value in the
corresponding FSR register being the address of the
data. The FSR is an 8-bit register and allows address-
ing anywhere in the 256-byte data memory address
range. For banked memory, the bank of memory
accessed is specified by the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
PIC17C7XX
7.4.2 INDIRECT ADDRESSING OPERATION
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two con-
trol bits associated with each FSR register. These two
bits configure the FSR register to:
• Auto-decrement the value (address) in the FSR
after an indirect access
• Auto-increment the value (address) in the FSR
after an indirect access
• No change to the value (address) in the FSR after
an indirect access
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPF and MOVFP instructions, where either
'p' or 'f' is specified as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
A simple program to clear RAM from 20h - FFh is
shown in Example 7-1.
EXAMPLE 7-1: INDIRECT ADDRESSING
MOVLW 0x20
;
MOVWF FSR0
; FSR0 = 20h
BCF ALUSTA, FS1 ; Increment FSR
BSF ALUSTA, FS0 ; after access
BCF ALUSTA, C ; C = 0
MOVLW END_RAM + 1 ;
LP CLRF INDF0, F
; Addr(FSR) = 0
CPFSEQ FSR0
; FSR0 = END_RAM+1?
GOTO LP
; NO, clear next
:
; YES, All RAM is
:
; cleared
© 1998 Microchip Technology Inc.
DS30289A-page 53