PIC17C7XX Datasheet, PDF (46/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
TABLE 7-3: SPECIAL FUNCTION REGISTERS
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
MCLR,
WDT
Unbanked
00h INDF0
01h FSR0
02h PCL
03h⁽¹⁾ PCLATH
04h ALUSTA
05h T0STA
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
OV
Z
DC
INTEDG T0SE
T0CS
T0PS3 T0PS2 T0PS1
T0PS0
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
C
1111 xxxx 1111 uuuu
— 0000 000- 0000 000-
06h⁽²⁾
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
—
—
STKAV GLINTD
TO
PD
POR
PEIF T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
BOR
INTE
--11 11qq --11 qquu
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Bank 0
10h
PORTA ^(4,6)
RBPU
—
RA5/TX1/
CK1
RA4/RX1/ RA3/SDI/
DT1
SDA
RA2/SS/
SCL
RA1/T0CKI
RA0/INT
0-xx 11xx 0-uu 11uu
11h DDRB
Data direction register for PORTB
1111 1111 1111 1111
12h
PORTB ⁽⁴⁾
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
xxxx xxxx uuuu uuuu
13h RCSTA1
SPEN RX9
SREN
CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00u
14h RCREG1
Serial port receive register
xxxx xxxx uuuu uuuu
15h TXSTA1
CSRC TX9
TXEN
SYNC
—
—
TRMT
TX9D 0000 --1x 0000 --1u
16h TXREG1
Serial Port Transmit Register (for USART1)
xxxx xxxx uuuu uuuu
17h SPBRG1
Baud Rate Generator Register (for USART1)
0000 0000 0000 0000
Bank 1
10h
11h
12h
13h
14h
DDRC ⁽⁵⁾
PORTC ^{(4, 5)}
DDRD ⁽⁵⁾
PORTD ^{(4, 5)}
DDRE ⁽⁵⁾
Data direction register for PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
Data direction register for PORTE
RC3/
AD3
RD3/
AD11
RC2/
AD2
RD2/
AD10
RC1/
AD1
RD1/
AD9
RC0/
AD0
RD0/
AD8
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- 1111 ---- 1111
15h
PORTE ^{(4, 5)}
—
—
—
—
RE3/
CAP4
RE2/WR
RE1/OE RE0/ALE ---- xxxx ---- uuuu
16h PIR1
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TX1IF
RC1IF x000 0010 u000 0010
17h PIE1
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX1IE
RC1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>
whose contents are updated from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or extended microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device reset, these pins are configured as inputs.
DS30289A-page 46
© 1998 Microchip Technology Inc.