PIC17C7XX Datasheet, PDF (141/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

15.2 MSSP I²C Operation
The MSSP module in I²C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit address-
ing. Appendix E: gives an overview of the I²C bus spec-
ification.
Refer to Application Note AN578, "Use of the SSP
Module in the I ²C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
FIGURE 15-13: I²C SLAVE MODE BLOCK
DIAGRAM
Internal
data bus
Read
Write
SCL
SDA
SSPBUF reg
shift
clock
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
PIC17C7XX
FIGURE 15-14: I²C MASTER MODE BLOCK
DIAGRAM
Read
SSPADD<6:0>
7
Baud Rate Generator
Internal
data bus
Write
SCL
SDA
SSPBUF reg
shift
clock
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and Stop bit
detect / generate
Set/Clear S bit
and
Clear/Set P, bit
(SSPSTAT reg)
and Set SSPIF
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I²C mode is enabled. The SSP
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON1<5>).
The MSSP module has six registers for I²C operation.
These are the:
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I²C oper-
ation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I²C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate DDR bits. Selecting an I²C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I²C mode.
© 1998 Microchip Technology Inc.
DS30289A-page 141