PIC17C7XX Datasheet, PDF (252/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
78
79
SDO
80
MSb
79
78
BIT6 - - - - - -1
LSb
SDI
MSb IN
74
73
Refer to Figure 20-1 for load conditions.
75, 76
BIT6 - - - -1
LSb IN
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
70 ^{TssL2scH, SS↓ to SCK↓ or SCK↑ input}
TssL2scL
TCY *
— — ns
71 ^TscH
71A
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 * — — ns
Single Byte
40
— — ns Note 1
72 ^TscL
72A
SCK input low time
(slave mode)
Continuous 1.25TCY + 30 * — — ns
Single Byte
40
— — ns Note 1
73 ^{TdiV2scH, Setup time of SDI data input to SCK}
TdiV2scL edge
100 *
— — ns
73A ^TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 * — — ns Note 1
edge of Byte2
74 ^{TscH2diL, Hold time of SDI data input to SCK edge}
TscL2diL
100 *
— — ns
75 ^TdoR
SDO data output rise time
—
10 25 * ns
76 ^TdoF
SDO data output fall time
—
10 25 * ns
78 ^TscR
SCK output rise time (master mode)
—
10 25 * ns
79 ^TscF
SCK output fall time (master mode)
—
10 25 * ns
80 ^{TscH2doV, SDO data output valid after SCK edge}
TscL2doV
—
— 50 * ns
*
Characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30289A-page 252
Preliminary
© 1998 Microchip Technology Inc.