PIC17C7XX Datasheet, PDF (257/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 20-14: I²C BUS DATA TIMING
103
100
101
SCL
SDA
In
90
91
106
107
109
109
SDA
Out
Note: Refer to Figure 20-1 for load conditions.
102
92
110
TABLE 20-14: I²C BUS DATA REQUIREMENTS
Param No. Sym Characteristic
Min
Max Units
Conditions
100
THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) § —
ms
400 kHz mode 2(TOSC)(BRG + 1) § —
ms
1 MHz mode ⁽¹⁾ 2(TOSC)(BRG + 1) § —
ms
101
TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) § —
ms
400 kHz mode 2(TOSC)(BRG + 1) § —
ms
1 MHz mode ⁽¹⁾ 2(TOSC)(BRG + 1) § —
ms
102
TR SDA and SCL 100 kHz mode
—
1000 * ns Cb is specified to be from
rise time
400 kHz mode
20 + 0.1Cb *
300 * ns 10 to 400 pF
1 MHz mode ⁽¹⁾
—
300 * ns
103
TF SDA and SCL 100 kHz mode
—
300 * ns Cb is specified to be from
fall time
400 kHz mode
20 + 0.1Cb *
300 * ns 10 to 400 pF
1 MHz mode ⁽¹⁾
—
100 * ns
90
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) § —
ms Only relevant for repeated
setup time
400 kHz mode 2(TOSC)(BRG + 1) § —
ms START condition
1 MHz mode ⁽¹⁾ 2(TOSC)(BRG + 1) § —
ms
91
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) § —
ms After this period the first
hold time
400 kHz mode 2(TOSC)(BRG + 1) § —
ms clock pulse is generated
1 MHz mode ⁽¹⁾ 2(TOSC)(BRG + 1) § —
ms
106
THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
1 MHz mode ⁽¹⁾
0
0
TBD *
—
ns
0.9 * ms
—
ns
107
TSU:DAT Data input
setup time
100 kHz mode
400 kHz mode
1 MHz mode ⁽¹⁾
250 *
100 *
TBD *
—
ns Note 2
—
ns
—
ns
92
TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) § —
ms
setup time
400 kHz mode 2(TOSC)(BRG + 1) § —
ms
1 MHz mode ⁽¹⁾ 2(TOSC)(BRG + 1) § —
ms
109
TAA Output valid
100 kHz mode
—
3500 * ns
from clock
400 kHz mode
—
1000 * ns
1 MHz mode ⁽¹⁾
—
—
ns
110
TBUF Bus free time
100 kHz mode
400 kHz mode
1 MHz mode ⁽¹⁾
4.7 ‡
1.3 ‡
TBD *
—
ms Time the bus must be free
—
ms before a new transmission
—
ms can start
D102 ‡
Cb Bus capacitive loading
—
400 * pF
* Characterized but not tested.
§ This specification ensured by design.
‡ These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast-mode (400 KHz) I²C-bus device can be used in a standard-mode I²C-bus system, but the parameter # 107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter # 102 + # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
3: C_b is specified to be from 10-400pF. The minimum specifications are characterized with C_b=10pF. The rise time spec (t_r)
is characterized with R_p=R_p min. The minimum fall time specification (t_f) is characterized with C_b=10pF, and R_p=R_p max.
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>)=1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R_p=R_p min and
C_b=400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
© 1998 Microchip Technology Inc.
Preliminary
DS30289A-page 257