PIC17C7XX Datasheet, PDF(295/328 Page) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

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PIC17C7XX Datasheet, PDF (295/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

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PIC17C7XX

FIGURE F-5: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)

R-0

PEIF

bit7

bit 7:

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

T0CKIF T0IF

INTF

PEIE T0CKIE T0IE

INTE

bit0

R = Readable bit

W = Writable bit

- n = Value at POR reset

PEIF: Peripheral Interrupt Flag bit

This bit is the OR of all peripheral interrupt ï¬ag bits ANDâed with their corresponding enable bits. The

interrupt logic forces program execution to address (20h) when a peripheral interrupt is pending.

1 = A peripheral interrupt is pending

0 = No peripheral interrupt is pending

bit 6:

T0CKIF: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).

1 = The software speciï¬ed edge occurred on the RA1/T0CKI pin

0 = The software speciï¬ed edge did not occur on the RA1/T0CKI pin

bit 5:

T0IF: TMR0 Overï¬ow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).

1 = TMR0 overï¬owed

0 = TMR0 did not overï¬ow

bit 4:

INTF: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).

1 = The software speciï¬ed edge occurred on the RA0/INT pin

0 = The software speciï¬ed edge did not occur on the RA0/INT pin

bit 3:

PEIE: Peripheral Interrupt Enable bit

This bit acts as a global enable bit for the peripheral interrupts that have their corresponding enable bits

set.

1 = Enable peripheral interrupts

0 = Disable peripheral interrupts

bit 2:

T0CKIE: External Interrupt on T0CKI Pin Enable bit

1 = Enable software speciï¬ed edge interrupt on the RA1/T0CKI pin

0 = Disable interrupt on the RA1/T0CKI pin

bit 1:

T0IE: TMR0 Overï¬ow Interrupt Enable bit

1 = Enable TMR0 overï¬ow interrupt

0 = Disable TMR0 overï¬ow interrupt

bit 0:

INTE: External Interrupt on RA0/INT Pin Enable bit

1 = Enable software speciï¬ed edge interrupt on the RA0/INT pin

0 = Disable software speciï¬ed edge interrupt on the RA0/INT pin

Â© 1998 Microchip Technology Inc.

DS30289A-page 295

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