PIC17C7XX Datasheet, PDF (261/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 20-19: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK
132
A/D DATA
ADRES
ADIF
GO
(TOSC/2) ⁽¹⁾
1 TCY
131
130
9
8
7 ^{... ...} 2
1
0
OLD_DATA
NEW_DATA
DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 20-20: A/D CONVERSION REQUIREMENTS
Param.
No.
130
131
132
Sym
TAD
TCNV
TACQ
Characteristic
A/D clock period
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
Conversion time
(not including acquisition time) (Note 1)
Acquisition time
Min
1.6
3.0
2.0 *
3.0 *
11 §
(Note 2)
Typ†
—
—
4.0
6.0
—
20
Max Units
Conditions
—
—
6.0 *
9.0 *
12 §
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
—
µs
134
*
†
§
Note 1:
10 *
—
—
µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
TGO Q4 to ADCLK start
—
Tosc/2 § —
— If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEP instruction to be exe-
cuted.
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
This specification ensured by design.
ADRES register may be read on the following TCY cycle.
© 1998 Microchip Technology Inc.
Preliminary
DS30289A-page 261