PIC17C7XX Datasheet, PDF (199/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
MSb
LSb ^Affected
Notes
TSTFSZ
f
Test f, skip if 0
1 (2) 0011 0011 ffff ffff
None 6,8
XORWF f,d Exclusive OR WREG with f
1 0000 110d ffff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b Bit Clear f
1 1000 1bbb ffff ffff
None
BSF
f,b Bit Set f
1 1000 0bbb ffff ffff
None
BTFSC
f,b Bit test, skip if clear
1 (2) 1001 1bbb ffff ffff
None 6,8
BTFSS
f,b Bit test, skip if set
1 (2) 1001 0bbb ffff ffff
None 6,8
BTG
f,b Bit Toggle f
1 0011 1bbb ffff ffff
None
LITERAL AND CONTROL OPERATIONS
ADDLW
k ADD literal to WREG
1 1011 0001 kkkk kkkk OV,C,DC,Z
ANDLW
k AND literal with WREG
1 1011 0101 kkkk kkkk
Z
CALL
k Subroutine Call
2 111k kkkk kkkk kkkk
None 7
CLRWDT — Clear Watchdog Timer
1 0000 0000 0000 0100
TO,PD
GOTO
k Unconditional Branch
2 110k kkkk kkkk kkkk
None 7
IORLW
k Inclusive OR literal with WREG
1 1011 0011 kkkk kkkk
Z
LCALL
k Long Call
2 1011 0111 kkkk kkkk
None 4,7
MOVLB
k Move literal to low nibble in BSR
1 1011 1000 uuuu kkkk
None
MOVLR
k Move literal to high nibble in BSR
1 1011 101x kkkk uuuu
None
MOVLW k Move literal to WREG
1 1011 0000 kkkk kkkk
None
MULLW
k Multiply literal with WREG
1 1011 1100 kkkk kkkk
None
RETFIE
— Return from interrupt (and enable interrupts)
2 0000 0000 0000 0101
GLINTD 7
RETLW
k Return literal to WREG
2 1011 0110 kkkk kkkk
None 7
RETURN — Return from subroutine
2 0000 0000 0000 0010
None 7
SLEEP
— Enter SLEEP Mode
1 0000 0000 0000 0011
TO, PD
SUBLW
k Subtract WREG from literal
1 1011 0010 kkkk kkkk OV,C,DC,Z
XORLW
k Exclusive OR literal with WREG
1 1011 0100 kkkk kkkk
Z
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
Refer to Table 18-1 for opcode field descriptions.
2’s Complement method.
Unsigned arithmetic.
If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of
the PC (PCL)
Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
Two-cycle instruction when condition is true, else single cycle instruction.
Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
A “skip” means that instruction fetched during execution of current instruction is not executed, instead an NOP is executed.
© 1998 Microchip Technology Inc.
DS30289A-page 199