PIC17C7XX Datasheet, PDF (151/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
A typical transmit sequence would go as follows:
a) The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
b) SSPIF is set. The module will wait the required
start time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
i) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
15.2.8 BAUD RATE GENERATOR
In I²C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-21). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY), on the
Q2 and Q4 clock.
In I²C master mode, the BRG is reloaded automati-
cally. If Clock Arbitration is taking place for instance,
the BRG will be reloaded when the SCL pin is sampled
high (Figure 15-22).
FIGURE 15-21: BAUD RATE GENERATOR
BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload Reload
Control
CLKOUT
Fosc/4
BRG Down Counter
FIGURE 15-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
BRG
value
BRG
reload
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements
(on Q2 and Q4 cycles)
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
© 1998 Microchip Technology Inc.
DS30289A-page 151