PIC17C7XX Datasheet, PDF (21/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

5.0 RESET
The PIC17CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR Reset
• WDT Reset
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state”. The TO and PD bits are set or cleared differently
in different reset situations as indicated in Table 5-3.
These bits, in conjunction with the POR and BOR bits,
are used in software to determine the nature of the
reset. See Table 5-4 for a full description of the reset
states of all registers.
PIC17C7XX
When the device enters the "reset state" the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impendance inputs. The reset state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
Note:
While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 5-1.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR Brown-out
Module _Reset
WDT
Module
WDT
Time_Out
Reset
VDD rise
detect _{Power_On_Reset}
S
VDD
OST/PWRT
OST
R
10-bit Ripple counter
OSC1
PWRT
On-chip
RC OSC†
10-bit Ripple counter
Chip_Reset
Q
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
© 1998 Microchip Technology Inc.
DS30289A-page 21