PIC17C7XX Datasheet, PDF (59/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

8.1 Table Writes to Internal Memory
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
The sequence of events for programming an internal
program memory location should be:
1. Disable all interrupt sources, except the source
to terminate EPROM program write.
2. Raise MCLR/VPP pin to the programming volt-
age.
3. Clear the WDT.
4. Do the table write. The interrupt will terminate
the long write.
5. Verify the memory location (table read).
Note 1: Programming requirements must be
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM loca-
tions that are not fully programmed and
may lose their state over time.
Note 2: If the VPP requirement is not met, the
table write is a 2 cycle write and the pro-
gram memory is unchanged.
PIC17C7XX
8.1.1 TERMINATING LONG WRITES
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the inter-
rupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
Note 1: If an interrupt is pending, the TABLWT is
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
Note 2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is
terminated. If GLINTD is clear, the program will vec-
tor, if GLINTD is set, the program will not vector to the
interrupt address.
TABLE 8-1: INTERRUPT - TABLE WRITE INTERACTION
Interrupt
Source
RA0/INT,
TMR0,
T0CKI
Peripheral
GLINTD
0
0
1
1
Enable
Bit
1
1
0
1
0
1
0
1
1
0
1
1
Flag
Bit
1
0
x
1
1
0
x
1
Action
Terminate long table write (to internal program memory),
branch to interrupt vector (branch clears flag bit).
None
None
Terminate long table write, do not branch to interrupt vec-
tor (flag is automatically cleared).
Terminate long table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt vector
(flag remains set).
© 1998 Microchip Technology Inc.
DS30289A-page 59