PIC17C7XX Datasheet, PDF (134/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 15-6: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN
bit7
bit 7:
ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
R = Readable bit
bit0 ^{W = Writable bit}
U = Unimplemented bit, Read
as ‘0’
- n = Value at POR reset
GCEN: General Call Enable bit (In I²C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6:
ACKSTAT: Acknowledge Status bit (In I²C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5:
ACKDT: Acknowledge Data bit (In I²C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4:
ACKEN: Acknowledge Sequence Enable bit (In I²C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically cleared by hard-
ware.
0 = Acknowledge sequence idle
Note: If the I²C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
bit 3:
RCEN: Receive Enable bit (In I²C master mode only).
1 = Enables Receive mode for I²C
0 = Receive idle
Note: If the I²C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
bit 2:
PEN: Stop Condition Enable bit (In I²C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
Note: If the I²C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
bit 1:
RSEN: Repeated Start Condition Enabled bit (In I²C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
Note: If the I²C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled)
bit 0:
SEN: Start Condition Enabled bit (In I²C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note: If the I²C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
DS30289A-page 134
© 1998 Microchip Technology Inc.