PIC17C7XX Datasheet, PDF (149/328 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

15.2.5 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I²C bus may be taken when the P
bit is set, or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
PIC17C7XX
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-20: SSP BLOCK DIAGRAM (I²C MASTER MODE)
Read
Internal
data bus
Write
SSPBUF
SDA
SDA in
MSb
SSPSR
shift
clock
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
SSPM3:SSPM0
SSPADD<6:0>
Baud
rate
generator
SCL in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
© 1998 Microchip Technology Inc.
DS30289A-page 149