1EDI2002AS_15 Datasheet, PDF (92/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Register Description
Primary Second Configuration Register
This register is used to select the configuration of the device. It can only be written if bit PCFG.CFG1 is set.
PCFG2
Primary Second Configuration Register
Offset
05_H
Wakeup Value
n.a.
Reset Value
0045_H
15
7
6
FEN
rw
0
r
STPDEL
rw
10
9
8
DOEN1
DIO1
rw
rw
2
1
0
LMI
P
rh
rh
Field
0
DOEN1
DIO1
FEN
STPDEL
LMI
Bits
15:10
9
8
7
6:2
1
Type
r
rw
rw
rw
rw
rh
Description
Reserved
Read as 0_B.
DOUT Output Primary Enable Bit
This bit is used to enable the DOUT signal.
0_B: DOUT is disabled (and in tristate).
1_B: DOUT is enabled (output).
Digital Channel Configuration
This bit field determines the direction of pin DIO1.
0_B: DIO1 is an input.
1_B: DIO1 is an output.
EN/FEN Mode Configuration
This bit determines the validity mode of a signal at pin
EN/FEN.
0_B: EN Mode active. A valid signal is defined as a high
level.
1_B: FEN Mode active. A valid signal is defined as a
periodic signal.
Shoot Through Protection Delay Configuration
This bit field determines the dead time for the shoot-
through protection (in number of OSC1 clock cycles).
00_H: 0 clock cycle.
01_H: 1 clock cycle.
...
1F_H: 31 clock cycles.
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0_B: Previous Message was processed correctly.
1_B: Previous Message was discarded.
Datasheet
92
Hardware Description
Rev. 3.1, 2015-07-30