1EDI2002AS_15 Datasheet, PDF (70/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Protection and Diagnostics
Note: Internal filter ensures that STPER is not set for glitches smaller than approximately 50ns.
The STP can be tested by applying non valid INSTP and INP and by checking bit PSTAT2.STP.
The STP can not be disabled. However, setting pin INSTP to V_GND1 deactivates de facto the function.
3.4.2 Gate Monitoring
The Gate Monitoring functionality is summarized in Table 3-9:
Table 3-9 Gate Monitoring Overview
Parameter
Short Description
Function
Monitors the waveform at pin GATE.
Periodicity
Timeout detection at every PWM command transition. Exact timing
measurement on request.
Action in case of failure event Flag PER.GER is set.
Programmability
No
In-System Testability
Yes
The goal of this function is to allow a plausibility check on the IGBT gate voltage signal waveform during a
switching sequence, for example in order to track degradations of the IGBT gate resistances.
The Gate Monitoring consists in two functions: Gate Timeout and Gate Timing Capture.
Gate Timeout
The Gate Timeout mechanism is active for both turn-on and turn-off sequence. At the beginning of a turn-on
sequence, an internal 8-bit timer (in the clock domain OSC2) is cleared and starts counting up. When the gate
voltage reaches V_GATE2, the timer stops. In case the timer overflows, flag PER.GER is set.
A similar mechanism is initiated at every turn-off sequence (regular or safe). When a hard transition occurs, an
internal timer is cleared starts counting up. When the gate voltage reaches the value V_GATE1, the timer stops. In
case the timer overflows, flag PER.GER is set.
The Gate Timeout mechanism is always active, except in OPM5 and OPM6. In OPM5 and OPM6, the Gate
Timeout mechanism is disabled during turn-on sequences. It works however normally for turn-off sequences
Gate Timing Capture
This function is armed when an SPI command sets bit PCTRL.GTCT. This sets both bits SGM1.GTCT1 and
SGM2.GTCT2 which indicates that the function is armed. At the next turn-on, respectively turn-off, sequence, a
timing measurement is performed. At the beginning of a turn-on sequence, bit field SGM2.VTOM2 is cleared and
the device starts incrementing an internal counter (in the clock domain of SSOSC2). When signal GATE reaches
voltage V_GATE2, the value of the timer is stored in bit field SGM2.VTOM2 and bit SGM2.GTCT2 is cleared. In case
the timer overflows, value FF_H is stored.
Similarly, at the hard transition of a turn-off sequence, bit field SGM1.VTOM1 is cleared and the device starts
incrementing an internal counter (in the clock domain of SSOSC2). When signal GATE reaches voltage V_GATE1,
the value of the timer is stored in bit field SGM1.VTOM1 and bit SGM1.GTCT1 is cleared. In case the timer
overflows, value FF_H is stored.
Datasheet
70
Hardware Description
Rev. 3.1, 2015-07-30