1EDI2002AS_15 Datasheet, PDF (112/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Register Description
Secondary Second Configuration Register
This register is used to select the configuration of the device. It can only be written if bit SCFG.CFG2 is set.
SCFG2
Secondary Second Configuration Register
Offset
15_H
Wakeup Value
n.a.
Reset Value
0001_H
15
14
Res
7
6
TTOND
rw
13
12
ISMEN OVLO3D
rw
rw
5
4
DSATL
rw
11
10
ACLPM
DIO2
rw
rw
3
2
0
r
9
8
TTOND
rw
1
0
LMI
P
rh
rh
Field
Res
ISMEN
OVLO3D
ACLPM
DIO2
TTOND
Bits
15:14
13
12
11
10
9:6
Type
rw
rw
rw
rw
rw
rw
Description
Reserved
This bit field is reserved. It should be written with 0_H.
IGBT State Monitoring Function Enable Bit
This bit enables the IGBT State Monitoring Function on
the secondary side.
0_B: Functionality is disabled.
1_B: Functionality is enabled.
OVLO3 Mode Configuration
This bit configures the operation of the OVLO3 function.
0_B: OVLO3 events are Events Class B.
1_B: OVLO3 events are warning events.
Active Clamping Mode
This bit determines the mode of operation of pin DACLP.
0_B: DACLP is active for Regular and Safe Turn-Off
sequences.
1_B: DACLP is active only in case of a Safe Turn-Off
sequence.
Digital Channel Configuration
This bit field determines the direction of pin DIO2.
0_B: DIO2 is an input.
1_B: DIO2 is an output.
TTON Delay Configuration
This bit field defines the TTON delay (in SSOSC2 clock
cycles). Writing 00_H to this field deactivates the TTON
function. If used, a minimal value of at least A_H has to be
programmed.
Datasheet
112
Hardware Description
Rev. 3.1, 2015-07-30