1EDI2002AS_15 Datasheet, PDF (49/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Functional Description
2.4.8
EN Signal Pin
The EN/FEN signal allows the logic on the primary side to have a direct control on the state of the device. A valid
signal has to be provided on this pin. A valid to invalid transition of the signal on pin EN/FEN generates an Event
Class A.
Pin EN/FEN should be driven actively by the external circuit. In case this pin is floating, an internal weak pull-down
resistor ensures that the signal is low.
Note: It should be noted that even if the signal at pin EN/FEN is valid, the device can still be in disabled state. This
may happen for example if another error is being detected
Depending on the value of bit PCFG2.FEN, two types of valid signals can be chosen from:
EN Mode
When the EN Mode is selected (bit PCFG2.FEN cleared), pin EN/FEN acts as an Enable pin. A valid EN/FEN
signal is defined as a digital High level. When EN/FEN is at Low level, the signal is considered as not valid and
the device is in Disabled State. In case of a High-to-Low transition, an Event Class A is generated.
FEN Mode
When the FEN Mode (bit PCFG2.FEN set) is selected, a valid signal is defined as a periodic clock signal. The
signal is constantly monitored by a watchdog unit. The watchdog evaluates the signal as valid if two consecutive
valid half-periods are detected.
If, after a valid signal has been recognized, a timing violation is detected by the watchdog, an Event Class A is
generated.
Every time an edge (rising or falling) is received, a counter is started. The counter is incremented at a frequency
of f_OSC1/8. The following edge is expected by the device during a window corresponding to the time between state
2 and state 6 of the counter. in case the edge comes too early or too late, an Event Class A is generated.
An Invalid to Valid transition of signal EN/FEN deactivates signals NFLTA and NFLTB (when the device is in
OPM3 or OPM5 only).
The levels read by the device at pin EN/FEN is given by bits PPIN.ENL. The validity status of EN/FEN signal is
given by bit PSTAT2.ENVAL.
2.4.9 Reset Events
A reset event sets the device and its internal logic in the default configuration. All user-defined settings are
overwritten with the default values. The list of reset events and their effect is summarized in Table 2-13.
Datasheet
49
Hardware Description
Rev. 3.1, 2015-07-30